Method and apparatus for channel encoding and decoding in a communication system using low-density p

专利摘要:
Abstract A method for channel encoding using a Low-Density Parity-Check (LDPC) code, the method comprising: dividing information bits into a plurality of bit groups; determining a number of 5 information bits to be shortened; determining a number of bit groups to be shortened based on the determined number of information bits to be shortened; shortening information bits in the determined number of bit groups according to a predetermined order; and LDPC encoding the shortened information bits, wherein the predetermined order is 1 8 1h bit group, 1 th bit group, 1 th bit group, 4 h bit group, 15 bit group, 1 4 th bit group, 1 3 th bit group, 1 2 th bit group, 3 rd bit group, 11h bit group, 0 th bit 10 group, 9 th bit group, 2 nd bit group, 8 th bit group, 7 th bit group, t bit group, 6 th bit group, 5th bit group, 1 9 th bit group, and 0 th bit group, when a codeword length is 16200, the information bits is 7200, and a modulation scheme is 64 Quadrature Amplitude Modulation (64-QAM). [Fig. 9] DETERMINE TX MODULATION SCHEME 901 READ COLUMN GROUP INFORMATION OF DVB-S2 LDPC CODE TO BE SUBJECT TO SHORTENING 903 DETERMINE CODEWORD LENGTH AND INFORMATION LENGTH OF SHORTENED LOPC CODE 905 DETERMINE VALUE A IN ACCORDANCE WITH SHORTENING STEP 1 907 SELECT (A+1)-COLUMN GROUP INFORMATION IN ACCORDANCE 909 WITH SHORTENING STEP 2 GENERATE SHORTENED LDPC CODE USING DVB-S2 LDPC CODE GENEARTION METHOD F 911 IN ACCORDANCE WITH SHORTENING STEP 3 GENERATE FINAL LDPC CODE BY APPLYING ADDITIONAL SHORTENING IN 913 ACCORDANCE WITH SHORTENING STEP 4 APPLY PUNCTURING IN LDPC 9 ENCODING PROCESS WHEN NECESSARY 915 [Fig. 10] 1040 - PARITY-CHECK MATRIX EXTRACTOR j 1 0 2 0 jSHORTENING PATTERN CONTROLLER ENCODERl
公开号:AU2013201428A1
申请号:U2013201428
申请日:2013-03-12
公开日:2013-04-04
发明作者:Jae-Yoel Kim；Kyung-Joong Kim；Hwan-Joon Kwon；Hak-Ju Lee；Seho Myung；Hyun-Koo Yang；Kyeong-Cheol Yang
申请人:Samsung Electronics Co Ltd；Academy Industry Foundation of POSTECH；
IPC主号:H03M13-11

专利说明:
METHOD AND APPARATUS FOR CHANNEL ENCODING AND DECODING IN A COMMUNICATION SYSTEM USING LOW-DENSITY PARITY-CHECK CODES Related Application 5 This application is a divisional application of Australian application no. 2009217934 the disclosure of which is incorporated herein by reference. Most of the disclosure of that application is also included herein, however, reference may be made to the specification of application no. 2009217934 to gain further understanding of the invention claimed herein. Technical Field 10 The present invention relates generally to a communication system using Low-Density Parity Check (LDPC) codes, and more particularly, to a channel encoding/decoding apparatus and method for generating LDPC codes having various codeword lengths and code rates from an LDPC code given in a high-order modulation scheme. Background Art 15 In wireless communication systems, link performance significantly decreases due to various noises in the channels, a fading phenomenon, and Inter-Symbol Interference (ISI). Therefore, in order provide high-speed digital communication systems, which require high data throughput and reliability, such as the next-generation mobile communication, digital broadcasting, and portable internet, it is important to develop technologies for overcoming the channel noises, fading, and ISI. Recently, an 20 intensive study of an error-correcting code has been conducted as a method for increasing communication reliability by efficiently recovering distorted information. The LDPC code, i.e., a type of error-correcting code, is generally defined as a parity-check matrix, and can be represented using a bipartite graph, which is referred to as a Tanner graph. The bipartite graph means that vertexes constituting the graph are divided into two different types, and the 25 LDPC code is represented with the bipartite graph composed of vertexes, some of which are called variable nodes and the other of which are called check nodes. The variable nodes are one-to-one mapped to the encoded bits. FIG. 1 illustrates an example of a parity-check matrix H, of the LDPC code having 4 rows and 8 columns. 30 Referring to FIG. 1, because the number of columns is 8, the parity-check matrix H is an LDPC code that generates a length-8 codeword, and the columns are mapped to 8 encoded bits. FIG. 2 illustrates a Tanner graph corresponding to the parity-check matrix H of FIG. 1. Referring to FIG. 2, the Tanner graph of the LDPC code includes 8 variable nodes x (202), x 2 (204), x 3 (206), x 4 (208), x 5 (210), x 6 (212), x 7 (214), and x 8 (216), and 4 check nodes 218, 220, 222, and 35 224. An ith column and a jth row in the parity-check matrix H 1 of the LDPC code are mapped to a variable node xi and ajth check node, respectively. In addition, a value of 1, i.e., a non-zero value, at the point where an i'h column and a j'h row in the parity-check matrix H 1 of the LDPC code cross each other, indicates that there is an edge between the variable node xi and thejh check node on the Tanner graph as illustrated in FIG. 2. 4131471_1 (GHMalters) P84758AU.1 a/3/2013 2 In the Tanner graph of the LDPC code, a degree of the variable node and the check node indicates the number of edges connected to each respective node, and the degree is equal to the number of non-zero entries in a column or row corresponding to the pertinent node in the parity-check matrix of the LDPC code. For example, in FIG. 2, degrees of the variable nodes xi (202), x 2 (204), x 3 (206), x 4 5 (208), x 5 (210), x6 (212), x 7 (214), and x 8 (216) are 4, 3, 3, 3, 2, 2, 2, and 2, respectively, and degrees of check nodes 218, 220, 222, and 224 are 6, 5, 5, and 5, respectively. In addition, the numbers of non-zero entries in the columns of the parity-check matrix H, of FIG. 1, which correspond to the variable nodes of FIG. 2, coincide with their degrees 4, 3, 3, 3, 2, 2, 2, and 2,.respectively, and the numbers of non-zero entries in the rows of the parity-check matrix H1 of FIG. 1, which correspond to the check nodes of FIG. 10 2, coincide with their degrees 6, 5, 5, and 5, respectively. In order to express degree distribution for the nodes of the LDPC code, a ratio of the number of degree-i variable nodes to the total number of variable nodes is defined as f;, and a ratio of the number of degree-j check nodes to the total number of check nodes is defined as g. For example, for the LDPC code corresponding to FIGs. 1 and 2, f 2 =4/8, f 3 =3/8, f 4 =1/8, and fi=O for if2, 3, 4; and g5=3/4, g,=1/4, 15 and gj=O for jf5, 6. When a length of the LDPC code, i.e., the number of columns, is defined as N, and the number of rows is defined as N/2, the density of non-zero entries in the entire parity-check matrix having the above degree distribution is computed as shown Equation (1). 2f/N + 3f 3 N+ 4fN 5.25 N-N/2 N ......... (1) In Equation (1), as N increases, the density of l's in the parity-check matrix decreases. 20 Generally, as for the LDPC code, because the codeword length N is inversely proportional to the density of non-zero entries, the LDPC code with a large N has a very low density of non-zero entries. The term "low-density" in the name of the LDPC code originates from the above-mentioned relationship. FIG. 3 schematically illustrates an LDPC code adopted as the standard technology in Digital Video Broadcasting-Satellite transmission 2 nd generation(DVB-S2), which is one of the European 25 digital broadcasting standards. In FIG. 3, N 1 and K, denote a codeword length and an information length (or length of information word) of an LDPC code, respectively, and (Ni-K) provides a parity length. Further, integers M, and q satisfy q=(Nj-K 1 )/Mi. Preferably, K 1
/M
1 is an integer. Referring to FIG. 3, a structure of a parity part, i.e., Kj* 1 t column through (NI-1)thcolumn, in the 30 parity-check matrix, has a dual diagonal shape. Therefore, as for degree distribution over columns corresponding to the parity part, all columns have a degree of 2, except for the last column having a degree of 1. In the parity-check matrix, an information part, i.e., 0 'h column through (KI-1)'" column, is created using the following rules. 35 Rule 1: A total of K 1 /Mi column groups is generated by grouping K 1 columns corresponding to the information word in the parity-check matrix into multiple groups each including Mi columns. A method for forming columns belonging to each column group follows Rule 2 below. 41314711 (GHMatters) P84758AU.1 8/03/2013 3 Rule 2: First, positions of l's in each 0 th column in ithcolumn groups (where i=1,...,K/M) are determined. When a degree of a 0" column in each it' column group is denoted by Di, if positions of (1 (2) k) R2(k= 1,2,.., D.) rows with 1 are assumed to be ,positions ' ' of rows with 1 are defined as shown in Equation (2), in a jh column (where j=1,2,...,M-1) in an i'h column group. pRk) =Rftl)+ mod(N
-K
1 ), k =1,2,..., Dj, i=1..,l/M1 , j=1,., M, - 1 5 .... (2) According to the above rules, it can be appreciated that degrees of columns belonging to an ith column group are all equal to Di. For a better understanding of a structure of a DVB-S2 LDPC code that stores information on the parity-check matrix according to the above rules, the following more detailed 10 example will be given. As a detailed example, for N 1 =30, K 1 =15, M]=5, and q=3, three sequences for the information on the positions of rows with 1 for 0 1h columns in 3 column groups can be expressed as follows. Herein, these sequences are referred to as "weight-I position sequences." R'= ,0 '1, l 0 R( = 0, R(" 11, R() =13 2,0 - ' 2,0 -b 2,0 R('= 0, R 2 10, R ) -14. 15 Regarding the weight-i position sequence for Q0h columns in each column group, only the corresponding position sequences can be expressed as follows for each column group. For example: 0 1 2 0 11 13 0 10 14. 20 That is, the i" weight-i position sequence in the i* line sequentially represents the information on the positions of rows with 1 for the i' 1 column group. It is possible to generate an LDPC code having the same concept as that of a DVB-S2 LDPC code illustrated FIG. 4, by forming a parity-check matrix using the information corresponding to the detailed example, and Rules 1 and 2. 25 It is known that the DVB-S2 LDPC code designed in accordance with Rules I and 2 can be efficiently encoded using the structural shape. Respective steps in a process of performing LDPC encoding using the DVB-S2 based parity-check matrix will be described below by way of example. In the following description, as a detailed example, a DVB-S2 LDPC code with N1=16200, Kj=10800,-M,=360, and q=1-5 undergoes an encoding process-For convenience-information-bits having- - 4131471_1 (GHMaflers) P84758AU.1 8/03/2f13 4 a length K, are represented as 0 1' a i -1 , and parity bits having a length (NI-K 1 ) are expressed as O , P1 . N1 -Ki 1 Step 1: An LDPC encoder initializes parity bits as follows: S P 1 - - - - Ni-KI-1 0 5 Step 2: The LDPC encoder reads information on rows where a 1 is located in a column group from a 0I weight-l position sequence out of the stored sequences indicating the parity-check matrix. 0 2084 1613 1548 1286 1460 3196 4297 2481 3369 3451 4620 2622 Ri4=0, R( 1 =-2048, R '=1613, R"V=1548, R(-1286, R19=1460, R 7 = 3196, R(=4297, R = 2481, R -3369 R -= 3451, R 1 =K 4620, R = 2622. 10 The LDPC encoder updates particular parity bits p in accordance with Equation (3), using the R zk 1 7 13 read information and the first information bit io. Herein, x is a value of 1,0 for p 0 = 0 (d)0 P2084 = 2064 O' '0 P1613 21613 0 P1548 = 1548 0+ 0 , P1286 = P1286 0, P1460 1460 0> -3196 P3196 P > I4297 24297 , 0 248 2481 ]3369 - 3369 PEt, P3451- P3451 +y0 1 24620 P4620 +IG0 P2622 - P2622 (3) P = p i 0 P P ®0n In Equation (3), can also be expressed as , and 15 represents binary addition. Step 3: The LDPC encoder determines a value of Equation (4) for the next 359 information bits im (where m=1, 2, ... , 359) after io. {X+ (mnmodMA/1) x q}mod(N - K ), M 1 =360, in 1,2,...,359 .. .. ... ...... .(4) R (k) (k =1, 2,1...,113) 20 In Equation (4), x is a value of R . It should be noted that Equation (4) has the same concept as Equation (2). 4131471_1 (GHMafters) P34758.AU.1 8(03/2013 5 Next, the LDPC encoder performs an operation similar to Equation (3) using the values found in Equation (4). That is, the LDPC encoder updates parity bits P(x+(m modMf)xq)mod(N -K) for i. For example, for m=l, i.e., for i 1 , the LDPC encoder updates parity bits P(r+g)mod(Ni-Kj) as defined in Equation (5). 5 5 '1 P2099 P2099 1) h1 1628 P1628 n 11 1563 =RP1563 1,P1301 PA301 0+ , P1475 =P1475 09 11 P3211 = 3211 1, P4312 4312 +0 1, P2496 = P2496 + 'l, P3384 P3384 1+ '1 23466 = 3466 1, P4635 P F4635 1 1, P2637 2637 e 1 (5) In Equation (5), q=15. The LDPC encoder performs the above process for m=1, 2, ..., 359, in the same manner as described above. Step 4: As in Step 2, the LDPC encoder reads information of the I weight-i position sequence R7~(k -1,) .. 13) 10 R for a 36l"information bit i3 60 , and updates a particular px, where x is R M The LDPC encoder updates (+(mmdM)xq)modN--K)711.= -6 -,3062 -... 719 by similarly applying Equation (4) to the next 359 information bits i 61 , i 36 2 , -, i 7 19 after i 360 . Step 5: The LDPC encoder repeats Steps 2, 3, and 4 for all groups each having 360 information 15 bits. Step 6: The LDPC encoder finally determines parity bits using Equation (6). pj=p np l, i=1,2,...,N -K -1 1.. ...... (6) The parity bits pi of Equation (6) have undergone LDPC encoding. As described above, DVB-S2 performs encoding as described in Steps 1 to 6. 20 In order to apply the LDPC code to the actual communication system, the LDPC code should be designed to be suitable for the data rate required in the communication system. Particularly, LDPC codes having various codeword lengths are needed to support various data rates according to the system requirements in an adaptive communication system employing Hybrid Automatic Retransmission reqQuest (HARQ) and Adaptive Modulation and Coding (AMC), and also in a communication system 25 supporting various broadcast services. However, as described above, the LDPC code used in the DVB-S2 system has only two types of codeword lengths due to its limited use; and each type of the LDPC code uses an independent parity check matrix. Accordingly, there is a long-felt need in the art for a method for supporting various 4131471 1 (GHMatlers) P84758.AU.1 &8032013 6 codeword lengths to increase extendibility and flexibility of the system. Particularly, in the DVB-S2 system, transmission of data having several hundreds to thousands of bits is needed for transmitting signaling information. However, because only 16200 and 64800 are available for a length of the DVB S2 LDPC code, there is a still a need for support of various codeword lengths. However, because storing 5 independent parity-check matrixes for respective codeword lengths of the LDPC code may reduce memory efficiency, there is also a need for a scheme capable of efficiently supporting various codeword lengths from the existing parity-check matrix, without requiring a new parity-check matrix. It is noted that reliabilities of bits included in high-order modulation symbols are different when high-order modulation is used in the communication system requiring an LDPC code with various 10 codeword lengths, unlike when the high-order modulation is applied in the communication system employing only Binary Phase Shift Keying (BPSK) or Quadrature Phase Shift Keying (QPSK). In order to demonstrate the reliability difference in high-order modulation, a description will now be made below as to signal constellations for Quadrature Amplitude Modulation (QAM), which is high-order modulation commonly used in communication systems. A QAM-modulated symbol includes 15 a real part and an imaginary part, and various modulation symbols can be generated by differentiating magnitudes and signs of their real parts and imaginary parts. QAM will be described together with QPSK modulation in order to more clearly provide the details of QAM characteristics. (a) of FIG. 5 schematically illustrates a signal constellation for a conventional QPSK modulation. 20 Referring to (a) of FIG. 5, yo determines a sign of a real part while y1 determines a sign of an imaginary part. That is, a sign of the real part is plus (+) for yo=0, and minus (-) for yo=1. Also, a sign of the imaginary part is plus (+) for y1=0, and minus (-) for y1=l. Because yo and y1 are equal in error occurrence probability, as they are sign indication bits that respectively indicate signs of the real part and the imaginary part, reliabilities of (yo, yi) bits corresponding to one modulation signal are equal in 25 QPSK modulation. For yo,q and yiq, the second subscript index q indicates a q'1l output of bits included in a modulation signal. (b) of FIG. 5 schematically illustrating a signal constellation for a conventional 16-QAM modulation. Referring to (b) of FIG. 5, (yo, y1, y2, y3) correspond to bits of one modulation signal. More 30 specifically, bits yo and Y2 determine a sign and a magnitude of the real part, respectively, while bits y1 and y3 determine a sign and a magnitude of the imaginary part, respectively. That is, yo and y1 determine signs of the real part and imaginary part of the modulation signal, while y2 and y 3 determine magnitudes of the real part and imaginary part of the modulation signal. Because distinguishing a sign of a modulated signal is easier than distinguishing a magnitude of the modulated signal, y2 and y 3 are higher 35 in error occurrence probability than yo and y 1 . Therefore, in terms of non-error occurrence probabilities (i.e., reliabilities) of the bits, yo=y > y2=y3. That is, bits (yo, y1, y2, y3), which are included in a QAM modulation signal, unlike those of a QPSK modulation signal, have different reliabilities. In 16-QAM modulation, among 4 bits constituting a signal, 2 bits determine signs of the real part and imaginary part of the signal and the remaining 2 bits only need to determine magnitudes of the 4131471_1 (GHMatters) P84758.AU.1 80M3/2013 7 real part and imaginary part of the signal. Thus, orders of (yo, y1, Y2, y3) and a role of each bit are subject to change. (c) of FIG. 5 schematically illustrates a signal constellation for a conventional 64-QAM modulation. 5 From among (yo, yi, y2, y3, y4, ys), which correspond to bits of one modulation signal, bits yo, y2, and y4 determine a magnitude and a sign of the real part, and yi, y3, and y5 determine a magnitude and a sign of the imaginary part. Here, yo and y1 determine signs of the real part and the imaginary part, respectively, and a combination of y2 and y4 and a combination of y3 and y 5 determine magnitudes of the real part and the imaginary part, respectively. As described above, because distinguishing signs of a 10 modulated signal is easier than distinguishing magnitudes of the modulated signal, reliabilities of yo and y, are higher than reliabilities of y2, y3, y4. and y5. The bits y2 and y 3 are determined depending on whether a magnitude of the modulated symbol is greater or less than 4, and the bits y4 and y 5 are determined according to whether the magnitude of the modulated symbol is closer to 4 or 0, with 2 centered therebetween, or closer to 4 or 8 with 6 centered. 15 Accordingly, a range in which the magnitude is determined by y2 and y3 is 4, while a range for y4 andy 5 is 2. Therefore, y2 and y3 is higher than y4 and y 5 in reliability. As a result, yo=y >y 2 =y 3 >y 4 =ysin terms of non-error occurrence probabilities (i.e., reliabilities) of the bits. In 64-QAM modulation, of 6 bits constituting a signal, 2 bits determine signs of the real part and imaginary part of the signal and 4 bits only need to determine magnitudes of the real part and 20 imaginary part of the signal. Accordingly, orders of (yo, y', Y2, y3, y4, ys) and a role of each bit are subject to change. Even in a signal constellation of 256-QAM or higher, the roles and reliabilities of bits constituting a modulation signal are different as described above. Accordingly, a detailed description thereof is to be omitted herein. . To summarize, in BPSK or QPSK modulation, it is not necessary to consider a modulation 25 scheme when determining shortening and puncturing patterns because as reliabilities of bits included in a symbol are equal, reliabilities of codeword bits are also equal in an LDPC codeword that has undergone shortening or puncturing. However, in high-order modulation such as 16-QAM, 64-QAM, and 256-QAM, because the roles and reliabilities of bits included in a symbol are different, when a modulation scheme and a signal constellation/bit mapping (bit mapping on the signal constellation) 30 scheme have been determined, reliability of each codeword bit in an LDPC codeword, after it undergoes shortening or puncturing, may be different from that of the LDPC codeword before it undergoes shortening or puncturing, Therefore, there is a demand for an apparatus and method for generating an LDPC code using shortening or puncturing in consideration of high-order modulation. 35 Summary of the Invention In accordance with a first aspect of an embodiment of the present invention, there is provided a method for channel encoding using a Low-Density Parity-Check (LDPC) code, the method comprising: dividing information bits into a plurality of bit groups; determining a number of information bits to be shortened; 4131471_1 (GHMatters) P64755.AU.1 /03/2013 8 determining a number of bit groups to be shortened based on the determined number of information bits to be shortened; shortening information bits in the determined number of bit groups according to a predetermined order; and 5 LDPC encoding the shortened information bits, wherein the predetermined order is 1 8 h bit group, 1 7 th bit group, 16t" bit group, 4 th bit group, 15* bit group, 14 'h bit group, 13 11 bit group, 12"1 bit group, 3d bit group, 111P bit group, 10th bit group, 9th bit group, 2"d bit group, 80' bit group, 7 th bit group, I' bit group, 6 bit group, 5"' bit group, 19th bit group, and 0"' bit group, when a codeword length is 16200, the information bits is 7200, and a 10 modulation scheme is 64 Quadrature Amplitude Modulation (64-QAM). In accordance with a second aspect of an embodiment of the present invention, there is provided a method for channel decoding using a Low-Density Parity-Check (LDPC) code, the method comprising: demodulating a received signal; 15 determining positions of shortened information bits; and decoding the demodulated signal based on the determined positions of shortened information bits, wherein determining positions of shortened information bits comprises: determining a number of information bits to be shortened; and 20 determining a number of bit groups to be shortened based on the determined number of information bits to be shortened; and acquiring a predetermined order of bit groups, wherein the predetermined order is 18h bit group, 1 7 th bit group, 16 'b bit group, 4th bit group, 15 th bit group, 14"' bit group, 1 3th bit group, 1 2 th bit group, 3 rd bit group, i1"' bit group, 10" bit group, 9th 25 bit group, 2 "d bit group, 8"' bit group, 71 bit group, l't bit group, 6th bit group, 5 th bit group, I 9 th bit group, and 0"' bit group, when a codeword length is 16200, the information bits is 7200, and a modulation scheme is 64 Quadrature Amplitude Modulation (64-QAM). - In accordance with a third aspect of an embodiment of the present invention, there is provided an apparatus for channel encoding using a Low-Density Parity-Check (LDPC) code, the apparatus 30 comprising: a parity-check matrix extractor arranged to divide information bits into a plurality of bit groups, determine a number of information bits to be shortened, determine a number of bit groups to be shortened based on the determined number of information bits to be shortened, and shorten information bits in the determined number of bit groups according to a predetermined order; and 35 LDPC encoder arranged to LDPC encode the shortened information bits, wherein the predetermined order is 1 8 th bit group, 17 'b bit group, 16 h bit group, 4 'h bit group, 15"h bit group, 14"' bit group, p bit group, 12r bit group, 3d bit group, I1t" bit group, 1 0 th bit group, 9 th bit group, 2 "d bit group, 8* bit group, 7h bit group, I' bit group, 6 th bit group, 5 th bit group, 19 ' bit group, and 0" bit group, when a codeword length is 16200, the information bits is 7200, and a 40 modulation scheme is 64 Quadrature Amplitude Modulation (64-QAM). 4131471_1 (GHMatters) PB475B.AU.1 B03/2013 9 In accordance with a fourth aspect of an embodiment of the present invention, there is provided an apparatus for channel decoding using a Low-Density Parity-Check (LDPC) code, the apparatus comprising: a demodulator arranged to demodulate a received signal; 5 a shortening pattern determiner arranged to determine positions of shortened information bits; and a decoder arranged to decode the demodulated signal based on the determined positions of shortened information bits, wherein the shortening pattern determiner determines the positions of shortened information bits 10 by: determining a number of information bits to be shortened; and determining a number of bit groups to be shortened based on the determined number of information bits to be shortened; and acquiring a predetermined order of bit groups, 15 wherein the predetermined order is 18"' bit group, 17'h bit group, 16"h bit group, 4th bit group, 15"' bit group, 14 'h bit group, 13 th bit group, 12' bit group, 3 rd bit group, I I 1h bit group, 1Oh bit group, 9"h bit group, 2 nd bit group, 8'h bit group, 7 th bit group, 1" bit group, 6' bit group, 5th bit group, 19t" bit group, and 0"' bit group, when a codeword length is 16200, the information bits is 7200, and a modulation scheme is 64 Quadrature Amplitude Modulation (64-QAM). 20 Advantageous Effects In an embodiment, the present invention can generate a separate LDPC code with a different codeword length using information on the parity-check matrix given in the communication system that uses high-order modulation and an LDPC code. . In addition, the embodiments of the present invention can perform shortening using different 25 shortening patterns according to modulation schemes. Description of Drawings The above and other aspects, features, and advantages of certain embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: 30 FIG. I illustrates an example of a parity-check matrix of a length-8 LDPC code; FIG. 2 illustrates a Tanner graph for a parity-check matrix of a length-8 LDPC code; FIG. 3 illustrates a schematic structure of a DVB-S2 LDPC code; FIG. 4 illustrates an example of a parity-check matrix of a DVB-S2 LDPC code; (a) of FIG. 5 schematically illustrates a signal constellation for a conventional QPSK 35 modulation used in a digital communication system; (b) of FIG. 5 schematically illustrates a signal constellation for a conventional 16-QAM modulation used in a digital communication system; (c) of FIG. 5 schematically illustrates a signal constellation for a conventional 64-QAM modulation used in a digital communication system; 40 FIG. 6 is a block diagram of a transceiver in a communication system using an LDPC code; 4131471_1 (GHMaters) P84758,AU.1 8/03/2013 10 (a) of FIG. 7 illustrates an example of signal constellation/bit mapping in 16-QAM modulation; (b) of FIG. 7 illustrates an example of signal constellation/bit mapping modified by shortening in 16-QAM modulation; (a) of FIG. 8 illustrates an example of signal constellation/bit mapping in 64-QAM modulation; 5 (b) of FIG. 8 illustrates an example of signal constellation/bit mapping modified by shortening in 64-QAM modulation; FIG. 9 illustrates a procedure for generating an LDPC code with a different codeword length from a parity-check matrix of a stored LDPC code according to an embodiment of the present invention; FIG. 10 illustrates a block diagram of a transmission apparatus using a proposed shortened 10 LDPC code according to an embodiment of the present invention; FIG. 11 illustrates a block diagram of a transmission apparatus using a proposed shortened/punctured LDPC code according to an embodiment of the present invention; FIG. 12 illustrates a block diagram of a reception apparatus using an LDPC code to which proposed shortening is applied, according to an embodiment of the present invention; 15 FIG. 13 illustrates a block diagram of a reception apparatus using an LDPC code to which proposed shortening and puncturing are both applied, according to an embodiment of the present invention; and FIG. 14 illustrates a flowchart of a reception operation of a reception apparatus according to an embodiment of the present invention. 20 Throughout the drawings, the same drawing reference numerals will be understood to refer to the same elements, features and structures. Mode for Invention The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of the embodiments of the invention as defined by the claims and their 25 equivalents. It includes various specific details to assist in that understanding, but these should not be construed as limitations. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness. 30 Further, the terms and words used in the following description and claims are not limited to the bibliographical meanings, but, are used by the inventor to enable a clear and consistent understanding of the present invention. Accordingly, it should be apparent to those skilled in the art that the following description of the embodiments of the present invention are provided for illustration purpose only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents. 35 The following description of the embodiments of the present invention provides a method for supporting an LDPC code with various codeword lengths suitable for high-order modulation, using a parity-check matrix of a structured LDPC code with a particular form. In addition, the description of the embodiments of the present invention provides an apparatus for supporting various codeword lengths according to high-order modulation in a communication system using an LDPC code in a particular 40 form, and a method for controlling the same. In particular, the description of the embodiments of the 4131471_1 (GHMalters) P8475.AU.1 D/03/2013 11 present invention provides a method for generating an LDPC code using a parity-check matrix of a given LDPC code, the generated LDPC code being smaller than the given LDPC code, and an apparatus thereof FIG. 6 is a block diagram of a transceiver in a communication system using an LDPC code. 5 Referring to FIG. 6, a message u is input to an LDPC encoder 611 in a transmitter 610 before being transmitted to a receiver 630. The LDPC encoder 611 encodes the input message u, and outputs the encoded signal c to a modulator 613. The modulator 613 modulates the encoded signal c, and transmits the modulated signal s to the receiver 630 over a wireless channel 620. A demodulator 631 in the receiver 630 demodulates the received signal r, and outputs the demodulated signal x to an LDPC 10 decoder 633. The LDPC decoder 633 decodes the demodulated signal x, resulting in an estimate of the message based on the data received through the wireless channel 620. The LDPC encoder 611 generates a parity-check matrix according to a codeword length required by a communication system, using a preset scheme. Particularly, in accordance with an embodiment of the present invention, an LDPC encoder will support various codeword lengths using the 15 LDPC code without the separate need for additional stored information. In accordance with an embodiment of the present invention, a method of acquiring various codeword lengths from a given LDPC code uses shortening or puncturing. Methods that optimize performance by applying shortening or puncturing to an LDPC code in accordance with a code rate or a codeword length are currently known. However, in most cases, because the known method of 20 determining the shortening and puncturing patterns performs the optimization process considering only Binary Phase Shift Keying (BPSK) or Quadrature Phase Shift Keying (QPSK), only one optimized shortening and/or puncturing pattern can exist for a given LDPC code. However, the puncturing and shortening patterns optimized when a signal constellation/bit mapping scheme has been determined in high-order modulation can be different from those for BPSK or 25 QPSK modulation. In BPSK or QPSK modulation, because reliabilities of bits included in a symbol are equal, reliabilities of codeword bits in an LDPC codeword after it undergoes shortening or puncturing are also equal. Consequently, there is no need to consider a modulation scheme in the process of determining the shortening and puncturing patterns. However, as described above, in high-order modulation such as 16 30 QAM, 64-QAM, and 256-QAM, because reliabilities of bits included in a symbol are different, when a modulation scheme and a signal constellation/bit mapping scheme have been determined, reliability of each codeword bit in an LDPC codeword after it undergoes shortening or puncturing may be different from that of the LDPC codeword before it undergoes shortening or puncturing. (a) of FIG. 7, (b) of FIG. 7, (a) of FIG. 8, and (b) of FIG. 8 illustrate bit mapping examples in 35 which bits are mapped to a symbol according to degrees of variable nodes in an LDPC codeword, for 16-QAM and 64-QAM, respectively. More specifically, (a) of FIG. 7 illustrates an example of signal constellation/bit mapping in 16-QAM modulation, and (b) of FIG. 7 illustrates an example of signal constellation/bit mapping modified by shortening in 16-QAM modulation. For convenience, an LDPC codeword is divided herein into an 8 or 12-bit partial block. 4131471_1 (GHMatlers) P84758.AU.1 8/03/2013 12 Referring to (a) of FIG. 7, yo and y1 indicate high-reliability bits that determine signs of a real part and an imaginary part in a 16-QAM symbol, respectively. That is, reliability relationship between the bits are Yo = Y> Y2= y3. In (a) of FIG. 7, because y' and y 3 are mapped to an LDPC codeword bit part corresponding to the highest-degree variable nodes, 1/2 of the highest-degree variable nodes are mapped 5 to a high-reliability part while the other 1/2 are connected to a low-reliability part. Assuming that the half of the highest-degree variable nodes have undergone shortening as illustrated in (b) of FIG. 7, when symbol bits corresponding to the non-shortened highest-degree variable node are considered in the shortened LDPC codeword, 7/8 of a highest-degree variable node is mapped to y3 and the other 1/8 is mapped to yi. That is, the bit ratio is very different from that before 10 the shortening. Similarly, (a) of FIG. 8 illustrates an example of signal constellation/bit mapping in 64-QAM modulation, and (b) of FIG. 8 illustrates an example of signal constellation/bit mapping modified by shortening in 64-QAM modulation. In (a) of FIG. 8, a reliability relationship between bits included in a symbol is yo= y1>y2= y3> 15 y4= y5. In this case, it can be appreciated that 1/3 of variable nodes with the highest degree in the LDPC codeword are mapped to the lowest-reliability bit y 5 . However, when 2/3 of the highest-degree variable nodes undergo shortening as illustrated in (b) of FIG. 8, it can be understood that 5/6 of the remaining non-shortened highest-degree variable node is mapped to the lowest-reliability bit y5, so that the bit ratio is different from that before the shortening. 20 When the high-order modulation scheme and the signal constellation/bit mapping scheme are fixed for a given LDPC code as described above, the shortening or puncturing pattern used in BPSK or QPSK modulation may not be suitable because a ratio of the LDPC codeword bit being mapped to each bit of a modulation symbol is very different according to the shortening technique. It is also known that in the case of an LDPC code, degree distribution of a parity-check matrix 25 of its optimized LDPC code is very different according to the modulation scheme. That is, degree distribution of an LDPC code optimized for BPSK or QPSK modulation and degree distributions of LDPC codes optimized for 16-QAM, 64-QAM, and 256-QAM are all different. For similar reasons, it is obvious that when it is assumed that an LDPC code having one degree distribution is given, the optimized shortening or puncturing pattern is different according to the high 30 order modulation scheme. Accordingly, a shortening pattern should be determined considering an intended modulation scheme in order to find an optimized shortening or puncturing pattern of an LDPC code. Shortening will be described below before a description of a method for determining a shortening or puncturing pattern in consideration of a modulation scheme is given. The term 35 "shortening" as used herein refers to a method that does not substantially transmit a specified part of an LDPC codeword, after generating the LDPC codeword from a given particular parity-check matrix by performing LDPC encoding. For a better understanding of shortening, a parity-check matrix of the DVB-S2 LDPC code illustrated in FIG. 3 will be described in more detail below. 4131471_1 (GHMatters) P84758AU.1 8/0312013 13 For the parity-check matrix of the DVB-S2 LDPC code illustrated in FIG. 3, the total length is NI, length-K information bits -1 corresponds to a front part of the parity 0,O Pl *-, PN -K-1) check matrix, and length-(NI-Ki) parity bits I corresponds to a rear part of the parity-check matrix. Commonly, information bits freely have a value of 0 or 1, and the 5 shortening technique restricts values of information bits in a particular part that is subject to shortening. For example, shortening N, information bits io to commonly means that . That is, by limiting values for N, information bits io through , to 0, the shortening technique can obtain the same effect as substantially not using Nleading columns in the parity-check matrix of the DVB-S2 LDPC code illustrated in FIG. 3. The term "shortening" actually originates from the above 10 described limitation operation. Therefore, applying shortening herein also means considering values of the shortened information bits, as 0. With respect to the shortening technique, when the system is set up, a transmitter and a receiver can share or generate the same position information for the shortened information bits. Therefore, though the transmitter has not transmitted the shortened bits, the receiver can perform decoding, already 15 knowing that information bits in the positions corresponding to the shortened bits have a value of 0. In the shortening technique, because a length of a codeword that the transmitter actually transmits is NI-N, and a length of an information word is Ki-N,, the code rate becomes (K 1 - N,)/(N 1 .. N), which is always less than the first given code rate KI/N,. Generally, a puncturing technique can be applied to both the information bits and the parity bits. 20 Although the puncturing technique and the shortening technique commonly reduce codeword lengths, the puncturing technique, unlike the shortening technique described above, does not limit values of particular bits. More specifically, the puncturing technique is simply a method for not transmitting particular information bits or a particular part of generated parity bits, such that a receiver can erase the 25 corresponding bits. That is, by simply not transmitting bits in Np predefined positions in a generated length-N, LDPC codeword, the puncturing technique obtains the same effect as that obtained by transmitting a length-(NI-Np) LDPC codeword. Because columns corresponding to the punctured bits in the parity-check matrix are all used intact in a decoding process, the puncturing technique is distinct from the shortening technique. 30 Further, in accordance with an embodiment of the present invention, because position information for the punctured bits can be shared or estimated in common by the transmitter and the receiver when the system is set up, the receiver may merely erase the corresponding punctured bits, before decoding. In the puncturing technique, because a length of a codeword that the transmitter actually 35 transmits is N 1 -N, and a length of an information word is constantly KI, the code rate becomes K 1
/(N,
Np), which is always greater than the first given code rate K 1 /N,. 4131471_1 (GHMatters) P84750.AU.1 803/2013 14 A description will now be made of a shortening technique and a puncturing technique suitable for the DVB-S2 LDPC code. The DVB-S2 LDPC code, as described above, is an LDPC code having a particular structure. Therefore, compared with the normal LDPC code, the DVB-S2 LDPC code is able to undergo more efficient shortening and puncturing. 5 For convenience of this example, it is assumed that the DVB-S2 LDPC code has a codeword length and an information length are N, and K 1 , respectively, and a codeword length and an information length of an LDPC code that are desired to be finally obtained from the DVB-S2 LDPC code using the shortening technique and the puncturing technique are N 2 and K 2 , respectively. If a definition of N-N 2 =N and K-K 2 =K is given, it is possible to generate the LDPC code 10 whose codeword length and information length are N 2 and K2, respectively, by shortening Kbits and puncturing (N-K) bits from the parity-check matrix of the DVB-S2 LDPC code. For the generated NI-K4 LDPC code with N>0 or K>0, because its code rate MNA is generally different from the code rate NA = KA KI/Nlof the DVB-S2 LDPC code, its algebraic characteristic changes. For , the LDPC code is generated by not performing shortening and puncturing or by performing only shortening. 15 However, regarding the DVB-S2 LDPC code, as described in Rules I and 2, as one Rf-j(k = 1,2.., Dil i=1 KjfM1, j= 0,...7M1 -) value corresponds to M 1 columns, a total of Kl/N1 column groups each have a structural shape. Therefore, the DVB-S2 LDPC code is equal to an R(k) LDPC code that does not use M, columns, if it does not use one value. The following shortening process, which will be described with reference to FIG. 9, is proposed considering such 20 characteristics. FIG. 9 illustrates a procedure for generating an LDPC code with a different codeword length from a parity-check matrix of a stored LDPC code according to an embodiment of the present invention. Referring to FIG. 9, an LDPC encoder determines a transmission modulation scheme for a symbol in step 901, and reads column group information of a DVB-S2 LDPC code to be subjected to 25 shortening in step 903. That is, the LDPC encoder reads stored parity-check matrix information. Thereafter, the LDPC encoder determines a codeword length N2and an information length K2based on the column group information of the DVB-S2 LDPC code in step 905. Thereafter, the LDPC encoder performs a shortening process of steps 907 to 913, in which the LDPC encoder performs shortening corresponding to a required information length of an LDPC code, based on the read information of the 30 stored parity-check matrix. Shortening Step 1: The LDPC encoder determines in step 907, where is a maximum integer which is less than or equal to x. 4131471_1 (GHMallers) P4758.AU.1 V1a3/2013 15 Shortening Step 2: The LDPC encoder selects a sequence for (A+ 1) column groups from among R )(i = 1,. K /M) '0 .column groups in step 909. The selected sequence is defined as . The LDPC encoder considers that there is no sequence for the remaining K /M - A -1 column groups except for the partial sequence 0 in the sequence 5 Shortening Step 3: The LDPC encoder determines positions of column groups corresponding to an information word of the DVB-S2 LDPC code from the sequence 4 of (A+1) column groups selected in Shortening Step 2, generating a shortened DVB-S2 LDPC code in step 911. It should be noted that the shortened LDPC code has an information length (A+i)M1, which is always greater than or equal to K2. 10 Shortening Step 4: The LDPC encoder additionally shortens (A+l)M 1
-K
2 columns from the shortened LDPC code generated in Shortening Step 3 in step 913. In Shortening Step 4, the additional shortening is more easily implemented if the process is sequentially performed from the rear or the front of the column group where the additional shortening is achieved. 15 As described above, an embodiment of the present invention applies an efficient shortening technique that does not use information on column groups of the DVB-S2 LDPC code depending on the structural features of the DVB-S2 LDPC code, compared with a conventional bit-by-bit shortening technique, which is commonly used for shortening of the DVB-S2 LDPC code. Selection criteria of a sequence for column groups can be summarized as follows in Step 2 in 20 the shortening process of the DVB-S2 LDPC code. Criterion 1: The LDPC encoder selects a shortening pattern sequence for column groups defined such -that optimal degree distribution obtainable by considering a modulation scheme given for a normal LDPC code with a codeword length N 2 and an information length K2 is as similar as possible to degree distribution of a shortened LDPC code with a codeword length N 2 and an information length K 2 , 25 obtained by performing shortening on a DVB-S2 LDPC code with a codeword length N 1 and an information length K1. Criterion 2: The LDPC encoder selects a shortening pattern sequence for column group b defined to provide a code having the good cycle characteristic on the Tanner graph among the shortened codes selected in Criterion 1. In accordance with an embodiment of the present invention, regarding a 30 criterion for a cycle characteristic, the LDPC encoder selects a sequence where the minimum-length cycle in the Tanner graph is as large as possible and the number of the minimum-length cycles is as small possible. The optimal degree distribution of the normal LDPC code in which the modulation scheme is considered, can be found out in Criterion 1 using a density evolution analysis method, various 35 implementations of which are known in the art. However, because the process of determining the degree distribution using the _density evolution method is. not essential to .the .understanding _of the present invention, a detailed description thereof will not be provided. 4131471.1 (GHMalters) PB4758.AU.1 8103/2013 16 If the number of all possible (shortening pattern) sequences for the column groups is not great, the LDPC encoder may select (shortening pattern) sequence for the column group having the best performance by fully searching all the sequences regardless of Criterionsl and 2. However, the selection criteria for column groups, applied in Shortening Step 2. for the DVB-S2 LDPC code enable to 5 efficiently select a (shortening pattern)by selecting an LDPC code satisfying the both conditions when the number of all possible (shortening pattern) sequences for the column group is too large. Criterion 1 and Criterion 2 are applied when N 2 and K 2 are fixed values. However, if values of
N
2 and K 2 required in the system are varying, the shortening patterns optimized according to the value of K 2 may have no correlation. That is, when the values of N 2 and K 2 required in the system are varying, 10 all of shortening patterns optimized according to the value of K 2 should be stored separately, for optimized performance. Therefore, for system efficiency, suboptimal shortening patterns can be found, as will be described below, when the values of N 2 and K 2 required in the system are varying. Finding A Suboptimal Shortening Pattern Sequence 15 Assuming that selection of one column group is needed for shortening, because the number of selectable column groups is only one, it is possible to select a column group having the best performance. When selection of two column groups is needed for shortening, one column group showing the best performance, together with the already selected column group, are selected from the remaining column groups. Similarly, when selection of i column groups is needed for shortening, one 20 column group having the best performance, together with (i-1) column groups selected in the previous step for shortening, are selected from the remaining column groups. Though the above method cannot guarantee optimal selection for all cases, it has relatively stable performance from the shortening pattern having one regular rule, regardless of the change in the value of K 2 .Therefore, the above-described the method has advantages of relatively stable performance 25 and easy storage of shortening patterns. A DVB-S2 LDPC code having a total of G column groups corresponding to information bits will be described below by way of example. Assuming that orders of column groups, which are subjected to shortening in accordance with the method of determining shortening patterns are set as B 1 ,
B
2 , B 3 , ..., Bx, when only the sequence meaning the orders of the column groups is stored, efficient 30 shortening is possible for an arbitrary K 2 through Shortening Step 1 to Shortening Step 4. In order to show an example of the difference between shortening patterns found according to respective modulation schemes using the above methods, Table 1A and Table lB below show shortening methods and shortening patterns suboptimized for BPSK/QPSK, 16-QAM, and 64-QAM modulations with regard to a DVB-S2 LDPC code with a codeword length N 1 =16200 and an 35 information length K 1 =7200. 4131471_1 (GHMatlter) P84758.AU.1 8103/2013 17 Table 1A Major variables of N 1 =16200, KI=7200, M 1 =360, q=25 DVB-S2 LDPC code Range of K 2 Shortening Method 1) For an integer m= 7200-K 2 , shorten all of m column [ 360 j 528!1(2<7200 groups corresponding to 4
(
0 )', n(l)h, ... , 7r(m~1)th rows, and additionally shorten 7200-Kr360m information bits from a column group corresponding to a 7r(m)Ih Tow. Here, n indicates a permutation function that means a shortening pattern, and the relationships are shown at the bottom of the table. However, when a part of a column group corresponding to a lr(18)=19h row is shortened, columns in the positions corresponding to 168 Bose-Chaudhuri-Hocquenghem (BCH) parity bits do not undergo shortening. 2) Shorten all column groups corresponding to n(0)'h, 168K2<528 n(l)h, ... 7 t(1 7 )'h rows, and shorten all columns except for columns in the positions corresponding to 168 BCH parity bits from a column group corresponding to a 7r(18)=19th Tow. Also, additionally shorten 528-K 2 information bits from a column group corresponding to a n(19)=O'h row. 4131471_1 (GHMatter) PS4758.AU.1 8/0312013 18 Table IB Relationship between' permutatiorrfunctions suboptimize d on BPSK/QP SK 7r(0) 7t(1) r(2) W(3) 7r(4) i(5) ir(6) ir(7) n(8) 7r(9) 18 17 16 15. 14 13 12. 11 4 1.0 7u(10) w(11) -K(12) -E(T3) -K(14) -n(15) -E(16) gT(17) -j(18) 7T(19) 9 8 3 2 7 6 5 1 19 0 Relationship between permutation functions suboptimize d on 16QAM x() (1 (2) 71(3) -n(4) xT(5) n(6) )T(7) 'n(8) 7c(q 18 17 16 15 14 13 12 11 4 10 7L(10) 71(11) ir(12) !f(13) n(14) n(15) 70(16) 21(17) 7E(18) x(19) 3 9 2 8 7 6 1 5 19 0 Relationship between permutation functions suboptimize d on 64QAM 71(0) 7(1) 7(2) x(3) -1(4) -A(5) 7E(6) 7E(7) 7r(8) -A(9) 4 3 18 17 2 16 15 14 13 12 7t(10) 7T(11) x(12) 71(13) -E(14) 7g(15) c(1,6) -n(17) 7(18) 7(19) 11 1.0 9 1 8 7 6 5 19 0. Referring to Table 1A and Table 18, it can be appreciated that when a length of information bits 5 to be shortened is determined, the shortening method is performed through a predetermined process regardless of the modulation scheme, but the relationships between permutation functions indicating optimized shortening patterns are all different according to modulation schemes. That is, when the shortening method is applied without considering the modulation scheme, significant performance degradation may occur according to modulation schemes. 10 The suboptimized shortening patterns shown in Table IB, found for the shortening method in Table 1A, may not be unique according to conditions for finding the shortening patterns. For example, several column groups may exist that show similar performance in the interim process described above, i.e., Finding A Suboptimal Shortening Pattern Sequence. In this case, because selection of the next column groups may differ according to selection of column groups, the suboptimized shortening 15 patterns may not be unique according to performance difference of the shortening process. Actually, shortening patterns shown in Table IC also provide excellent performance, similar to the shortening method performance shown in Table IA. 4131471_1 (GHMalters) P84758.AU.1 8/0312013 19 Table IC Relationship between permutation functions suboptimize d on-BPSK/QPSK (2) 'a(0) 71(1) r(2) 7[(3) r(4) 7r(5) 2r(6) r(7) q(8) -A(9) 18 17 16 15 14 13 12 11 4 10 -(1O) 7(11) -g(12) -g(13) 7r(14) 7r(15) iE(16) 7c(17) -g(18) z(19) 9 8 3 2 7 6 5 1 19 0. Relationship between permutation functions suboptimize d on 16QAM (2) r(0) x(1) -g(2) 7r(3) r(4) -(5) 7r(6) -n(7) 7K(8) n(9) 18 17 16 15 14 13 12 11 4 10 -g(10) 7(11) 71(12) 7(13) (14) 7(15) 7K(16) )(17) 7(18) 7r(19) 9 8 7 3 2 1 6 5 19 0 Relationship between permutation ftinctions -suboptimize d on 64QAM (2) 7(0) 7(1) 7(2) 71(3) -g(4) 7r(5) r(6) x(7) -g(8) g(9) 18 17 16 4 15 14 13 12 3 11 7r(10) 7r(11) 7(12) 7A(13) 7r(14) 7(15) 7(16) -K(17) 7R(18) 7E(19) 10 9 2 8 7 1 6 5 19 0 The bit mapping methods corresponding to the signal constellations used in 16-QAM and 64 5 QAM modulations of Table 1C are the results obtained by applying the same bit mapping methods as those illustrated in (a) of FIG. 7, (b) of FIG. 7, (a) of FIG. 8, and (b) of FIG. 8. Referring back to FIG. 9, after step 913, when puncturing is needed, the LDPC encoder applies puncturing in the LDPC encoding process in step 915. The puncturing method will now be described below. 10 Assuming that a codeword length and an information length of an LDPC code are N 2 and K 2 , respectively, that the invention desires to finally obtain from the DVB-S2 LDPC code whose codeword length and information length are N, and K 1 , respectively, using the shortening technique and the puncturing technique, and that a definition of N-N 2 =N and K-K 2 =K is given, it is possible to generate the LDPC code having a codeword length and information length of N 2 and K 2 , respectively, by 15 shortening K bits and puncturing (N-K) bits from the parity-check matrix of the DVB-S2 LDPC code. For convenience, when it is assumed that the puncturing technique is applied only to the parity part, there is a possible method for puncturing 1 bit from the parity part every (N-K 1 )/(N-K) bits because the parity length is N 1 -K,. However, various other puncturing methods are also available. FIG. 10 illustrates a block diagram of a transmission apparatus using a shortened LDPC code 20 according to an embodiment of the present invention. 4131471_1 (GHMattOes) P84758AU1 8/032013 20 Referring to FIG. 10, a transmission apparatus includes a controller 1010, a shortening pattern applier 1020, an LDPC code parity-check matrix extractor 1040, and an LDPC encoder 1060. The LDPC code parity-check matrix extractor 1040 extracts an LDPC code parity-check matrix that has undergone shortening. The LDPC code parity-check matrix can be extracted using a memory, can be 5 given in the transmission apparatus, or can be generated in the transmission apparatus. In addition, the LDPC code parity-check matrix extractor 1040 determines a transmission modulation scheme for a transmission symbol, groups columns corresponding to an information word in the parity-check matrix of the LDPC code into a plurality of column groups, and orders the column groups. The shortening pattern applier 1020 determines a range of an information word it desires to 10 obtain through shortening, and based on the range of the information word, performs column group-by column group shortening on the column groups in an order according to a shortening pattern determined in consideration of the determined modulation scheme. The controller 1010 controls the shortening pattern applier 1020 to determine a shortening pattern according to the transmission modulation scheme and the information length, and the shortening 15 pattern applier 1020 inserts bits having a value of 0 in positions corresponding to the shortened bits, or removes columns corresponding to the shortened bits from a parity-check matrix of a given LDPC code. The shortening pattern can be a shortening pattern stored in a memory, generated using a sequence generator (not shown), or acquired using a density evolution analysis algorithm for a parity-check matrix and a given information length. 20 The LDPC encoder 1060 performs encoding based on the LDPC code shortened by the controller 1010 and the shortening pattern applier 1020. FIG. 11 illustrates a block diagram of a transmission apparatus for a DVB-S2 LDPC code using both shortening and puncturing. More specifically, the transmission apparatus of FIG. I1 also includes a puncturing pattern applier 1180 when compared to the transmission apparatus of FIG. 10. 25 Referring to FIG. 11, shortening is performed at an input stage of the LDPC encoder 1060, and puncturing is performed at an output stage of the LDPC encoder 1060. The puncturing pattern applier 1180 applies puncturing to an output of the LDPC encoder 1060. The method of applying puncturing has been described above in step 915 of FIG. 9. FIG. 12 illustrates a block diagram of a reception apparatus using an LDPC code to which 30 shortening is applied, according to an embodiment of the present invention. More specifically, FIG. 12 illustrates an example of a reception apparatus that receives a signal transmitted from a communication system using the shortened DVB-S2 LDPC code, and recovers user-desired data from the received signal when it detects a transmission modulation scheme and a length of the shortened DVB-S2 LDPC code from the received signal. 35 Referring to FIG. 12, the reception apparatus includes a controller 1210, a shortening pattern determination/estimation unit 1220, a demodulator 1230, and an LDPC decoder 1240. The demodulator 1230 receives and demodulates a shortened LDPC code, and provides the demodulated signal to the shortening pattern determination/estimation unit 1220 and the LDPC decoder 1240. The shortening pattern determination/estimation unit 1220, under the control of the controller 1210, estimates or 40 determines information on a shortening pattern of an LDPC code from the demodulated signal, and 4131471_1 (GHMatters) P84758,AU 510312D13 21 provides position information of the shortened bits to the LDPC decoder 1240. Determining or estimating the shortening patterns in the shortening pattern determination/estimation unit 1220 can use shortening patterns stored in a memory, can generate shortening patterns using a sequence generator (not shown), or can obtain shortening patterns using a density evolution analysis algorithm for a parity S check matrix and a given information length. The controller 1210 controls the shortening pattern determination/estimation unit 1220 to deliver a shortening pattern to the LDPC decoder 1240 depending on the modulation scheme and the information length. Because the probability that values of the shortened bits will be zero is 1 (i.e., 100%), the LDPC decoder 1240 determines whether or not it will allow the shortened bits to take part in 10 its decoding operation depending on the value 1 of the probability that the shortened bits would be zero. When the LDPC decoder 1240 receives information on a length of the DVB-S2 LDPC code shortened by the shortening pattern determination/estimation unit 1220, it restores the user-desired data from the received signals. FIG. 13 illustrates a block diagram of a reception apparatus using an LDPC code to which 15 shortening and puncturing are applied, according to an embodiment of the present invention. More specifically, the reception apparatus illustrated FIG. 13 includes a shortening/puncturing pattern determination/estimation unit 1320 that replaces the shortening pattern determination/estimation unit 1220 in the reception apparatus illustrated in FIG. 12. Referring to FIG. 13, when both shortening and puncturing are applied in the transmission 20 apparatus, the shortening/puncturing pattern determination/estimation unit 1320 in the reception apparatus may perform pattern determination or estimation on the shortening first, perform pattern determination or estimation on the puncturing first, or make pattern determination or estimation on both the shortening and puncturing. The LDPC decoder 1240 should have information about both shortening and puncturing to 25 perform decoding. FIG. 14 illustrates a flowchart of a reception operation of a reception apparatus according to an embodiment of the present invention. Referring to FIG. 14, a demodulator 1230 receives and demodulates a shortened LDPC code in step 1401. In step 1403, a shortening pattern determination/estimation unit 1220 determines or estimates 30 shortening/puncturing patterns from the demodulated signal. The shortening pattern determination/estimation unit 1220 determines in step 1405 whether there are any shortened or punctured bits. If there are no shortened or punctured bits, an LDPC decoder 1240 performs decoding in step 1411. However, if there are shortened or punctured bits, the shortening pattern determination/estimation unit 1220 delivers position information of the shortened/punctured bits 35 to the LDPC decoder 1240 in step 1407. - In step 1409, based on the position information of the shortened/punctured bits, the LDPC decoder 1240 determines that the probability that values of the shortened bits will be 0 is 1, and determines that the punctured bits are erased bits. Thereafter, the LDPC decoder 1240 performs LDPC decoding in step 1411. 4131471_1 (GHMatters) PS4758.AU.1 8/0312013 22 While the present invention has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims. 5 In the claims which follow and in the preceding description of the invention, except where the context requires otherwise due to express language or necessary implication, the word "comprise" or variations such as "comprises" or "comprising" is used in an inclusive sense, i.e. to specify the presence of the stated features but not to preclude the presence or addition of further features in various embodiments of the invention. 10 It is to be understood that, if any prior art publication is referred to herein, such reference does not constitute an admission that the publication forms a part of the common general knowledge in the art, in Australia or any other country. 4131471_1 (GHMatters) P84758.AU.1 8/0312013

权利要求:
Claims (16)
[1] 1. A method for channel encoding using a Low-Density Parity-Check (LDPC) code, the method comprising: 5 dividing information bits into a plurality of bit groups; determining a number of information bits to be shortened; determining a number of bit groups to be shortened based on the determined number of information bits to be shortened; shortening information bits in the determined number of bit groups according to a 10 predetermined order; and LDPC encoding the shortened information bits, wherein the predetermined order is 1 8 1h bit group, 1 7 h bit group, 1 6 h bit group, 4 h bit group, 1 5 th bit group, 1 4 th bit group, 1 3 th bit group, 1 2 th bit group, 3 d bit group, 11h bit group, I 0 th bit group, 9 th bit group, 2 "d bit group, 8 th bit group, 7 th bit group, t bit group, 6 th bit group, 5 th bit group, 9 th bit 15 group, and 0 th bit group, when a codeword length is 16200, the information bits is 7200, and a modulation scheme is 64 Quadrature Amplitude Modulation (64-QAM).
[2] 2. The method of claim 1, further comprising: determining a number of information bits to be obtained by shortening for determining the 20 number of information bits to be shortened.
[3] 3. The method of claim 1, comprising: when a number of bits of each bit group is 360 and the information bits is 7200, shortening all information bits in bit groups from 0 th bit group to (mtj/h bit group in the 25 predetermined order; and shortening (7200-K 2 -360m) information bits in mth bit group in the predetermined order, wherein, K 2 is a number of information bits to be obtained by shortening, (7200-K 2 ) is the number of m =7200 - K 2 information bits to be shortened, and L 360 J 30
[4] 4. A method for channel decoding using a Low-Density Parity-Check (LDPC) code, the method comprising: demodulating a received signal; determining positions of shortened information bits; and decoding the demodulated signal based on the determined positions of shortened information 35 bits, wherein determining positions of shortened information bits comprises: determining a number of information bits to be shortened; and determining a number of bit groups to be shortened based on the determined number of information bits to be shortened; and 24 acquiring a predetermined order of bit groups, wherein the predetermined order is 1 8 1h bit group, 1 7 h bit group, 1 6 h bit group, 4 h bit group, 1 5 th bit group, 1 4 th bit group, 1 3 th bit group, 1 2 th bit group, 3 rd bit group, 11h bit group, I 0 th bit group, 9 th bit group, 2 "d bit group, 8 th bit group, 7 th bit group, t bit group, 6 th bit group, 5 th bit group, 9 th bit 5 group, and 0 th bit group, when a codeword length is 16200, the information bits is 7200, and a modulation scheme is 64 Quadrature Amplitude Modulation (64-QAM).
[5] 5. The method of claim 4, wherein determining position of shortened information bits further comprising: 10 determining a number of information bits to be obtained by shortening for determining the number of information bits to be shortened.
[6] 6. The method of claim 4, comprising: when a number of bits of each bit group is 360 and the information bits is 7200, 15 determining that all information bits in bit groups from 0 th bit group to (Mtjjh bit group in the predetermined order is shortened; and determining that (7200-K 2 -360m) information bits in mth bit group in the predetermined order is shortened, wherein, K 2 is a number of information bits to be obtained by shortening, (7200-K 2 ) is the m7200 - K 2 20 number of information bits to be shortened, and L 360
[7] 7. An apparatus for channel encoding using a Low-Density Parity-Check (LDPC) code, the apparatus comprising: a parity-check matrix extractor arranged to divide information bits into a plurality of bit groups, 25 determine a number of information bits to be shortened, determine a number of bit groups to be shortened based on the determined number of information bits to be shortened, and shorten information bits in the determined number of bit groups according to a predetermined order; and LDPC encoder arranged to LDPC encode the shortened information bits, wherein the predetermined order is 1 8 1h bit group, 1 7 h bit group, 1 6 h bit group, 4 h bit group, 30 1 5 th bit group, 1 4 th bit group, 1 3 th bit group, 1 2 th bit group, 3 rd bit group, 1 1 th bit group, I 0 th bit group, 9 th bit group, 2 "d bit group, 8 th bit group, 7 th bit group, t bit group, 6 th bit group, 5 th bit group, 9 th bit group, and 0 th bit group, when a codeword length is 16200, the information bits is 7200, and a modulation scheme is 64 Quadrature Amplitude Modulation (64-QAM). 35
[8] 8. The apparatus of claim 7, wherein the shortening pattern applier is configured to determine a number of information bits to be obtained by shortening for determining the number of information bits to be shortened. 25
[9] 9. The apparatus of claim 7, further comprising means for, when a number of bits of each bit group is 360 and the information bits is 7200, shortening all information bits in bit groups from 0 h bit group to (m-1)th bit group in the predetermined order; and shortening (7200-K 2 -360m) information bits in mth bit group in the predetermined order, 5 wherein, K 2 is a number of information bits to be obtained by shortening, (7200-K 2 ) is the 17200 - K2 number of information bits to be shortened, and _ 360
[10] 10. An apparatus for channel decoding using a Low-Density Parity-Check (LDPC) code, the apparatus comprising: 10 a demodulator arranged to demodulate a received signal; a shortening pattern determiner arranged to determine positions of shortened information bits; and a decoder arranged to decode the demodulated signal based on the determined positions of shortened information bits, 15 wherein the shortening pattern determiner determines the positions of shortened information bits by: determining a number of information bits to be shortened; and determining a number of bit groups to be shortened based on the determined number of information bits to be shortened; and 20 acquiring a predetermined order of bit groups, wherein the predetermined order is 1 8 1h bit group, 1 th bit group, 1 th bit group, 4 h bit group, 1 5 th bit group, 1 4 th bit group, 1 3 th bit group, 1 2 th bit group, 3 rd bit group, 1 1 th bit group, I 0 th bit group, 9 th bit group, 2 "d bit group, 8 th bit group, 7 th bit group, t bit group, 6 th bit group, 5 th bit group, 9 th bit group, and 0 th bit group, when a codeword length is 16200, the information bits is 7200, and a 25 modulation scheme is 64 Quadrature Amplitude Modulation (64-QAM).
[11] 11. The apparatus of claim 10, wherein the shortening pattern applier is configured to determine a number of information bits to be obtained by shortening for determining the number of information bits to be shortened. 30
[12] 12. The apparatus of claim 10, further comprising means for, when a number of bits of each bit group is 360 and the information bits is 7200, determining that all information bits in bit groups from 0 th bit group to (m-1)th bit group in the predetermined order is shortened; and determining that (7200-K 2 360m) information bits in mth bit group in the predetermined order is shortened, 35 wherein, K 2 is a number of information bits to be obtained by shortening, (7200-K 2 ) is the 17200 - K 2 number of information bits to be shortened, and L 360 26
[13] 13. A method for channel encoding, substantially as herein described with reference to Figures 6 to 14 of the accompanying drawings.
[14] 14. A method for channel decoding, substantially as herein described with reference to Figures 6 to 5 14 of the accompanying drawings.
[15] 15. An apparatus for channel encoding, substantially as herein described with reference to Figures 6 to 14 of the accompanying drawings. 10
[16] 16. An apparatus for channel decoding, substantially as herein described with reference to Figures 6 to 14 of the accompanying drawings.

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同族专利:

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公开号 | 公开日

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AU2013201428B2|2015-03-19|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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KR100946884B1|2005-07-15|2010-03-09|삼성전자주식회사|Channel interleaving/de-interleaving apparatus in a communication system using a low density parity check code and control method thereof|

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KR100856235B1|2005-09-26|2008-09-03|삼성전자주식회사|Apparatus and method for encoding and decoding block low density parity check codes with a variable coding rate|

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法律状态:
2015-07-16| FGA| Letters patent sealed or granted (standard patent)|

优先权:

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申请号 | 申请日 | 专利标题

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KR10-2008-0017279||2008-02-26||

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KR10-2008-0022484||2008-03-11||

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KR10-2008-0025144||2008-03-18||

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AU2009217934A|AU2009217934B2|2008-02-26|2009-02-26|Method and apparatus for channel encoding and decoding in a communication system using Low-Density Parity-Check codes|

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AU2013201428A|AU2013201428B2|2008-02-26|2013-03-12|Method and apparatus for channel encoding and decoding in a communication system using low-density parity-check codes|AU2013201428A| AU2013201428B2|2008-02-26|2013-03-12|Method and apparatus for channel encoding and decoding in a communication system using low-density parity-check codes|